1 document # sram103 rev a revised october 2005 p4c147 ultra high speed 4k x 1 static cmos ram features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25 ns (commercial) ? 15/20/25/35 ns (military) low power operation ? 715 mw active ?10 (commercial) ? 550 mw active ?25 (commercial) ? 110 mw standby (ttl input) ? 55 mw standby (cmos input) single 5v 10% power supply separate input and output ports three-state outputs fully ttl compatible inputs and outputs standard pinout (jedec approved) ? 18 pin 300 mil dip ? 18 pin cerpack ? 18 pin lcc (290 x 430 mils) ? 18 pin lcc (295 x 335 mils) description the p4c147 is a 4,096-bit ultra high speed static ram organized as 4k x 1. the cmos memory requires no clocks or refreshing, and have equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v 10% tolerance power supply. access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is utilized to reduce power consumption in both active and standby modes. in addition to very high performance, this device features latch-up protection and single-event-upset protection. the p4c147 is available in 18 pin 300 mil dip packages, an 18-pin cerpack package, and 2 different lcc packages. functional block diagram pin configurations dip (p1, d1, c9), cerpack (f1) similar lcc (l7, l7-1)
p4c147 page 2 of 10 document # sram103 rev a maximum ratings (1) symbol parameter value unit v cc power supply pin with ? 0.5 to +7 v respect to gnd terminal voltage with ? 0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ? 55 to +125 c symbol parameter value unit t bias temperature under ? 55 to +125 c bias t stg storage temperature ? 65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) grade (2) commercial military symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf ambient temp 0c to 70c -55c to +125c gnd 0v 0v v cc 5.0v 10% 5.0v 10% recommended operating conditions v oh v ol v ih v il i li i lo i sb i sb1 parameter symbol output high voltage (ttl load) output low voltage (ttl load) input high voltage input low voltage input leakage current output leakage current standby power supply current (ttl input levels) standby power supply current (cmos input levels) test conditions i oh = ?4 ma, v cc = min. i ol = +8 ma, v cc = min v cc = max., v in = gnd to v cc ce v ih , v cc = max., mil. f=max., output open comm?l ce v hc , v cc = max., f= 0, mil. output open comm?l v in 0.2v or v in v cc -0.2v p4c147 min. 2.4 2.2 ?0.5 (3) __ __ __ __ dc electrical characteristics over recommended operating temperature and supply voltage (2) max. v cc =+0.5 0.8 30 23 15 10 unit v v v ma ma a a v 0.4 symbol parameter dynamic operating current unit -35 -25 -20 -15 -12 commercial military temperature range i cc power dissipation characteristics vs. speed 130 n/a 130 n/a 120 145 115 135 100 125 n/a 120 ma ma -10 mil. comm?l ?10 ?5 +10 +5 mil. comm?l ?10 ?5 +10 +5 v cc = max., ce = v ih , v out = gnd to v cc
p4c147 page 3 of 10 document # sram103 rev a min notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. ce is low and we is high for read cycle. 6. we is high, and address must be valid prior to or coincident with ce transition low. 7. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. 8. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 2 (6) timing waveform of read cycle no. 1 (5) sym. t rc t aa t ac t hz t pu t pd read cycle time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z chip enable to power up time chip disable to power down time -10 -12 -15 -20 -25 -35 unit ns ns ns ns ns ns ns ns min max 10 10 4 10 10 2 2 0 ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) 12 2 2 0 max 12 12 5 12 min 15 2 2 0 max 15 15 6 15 min 20 2 2 0 max 20 20 8 20 min 25 2 2 0 max 25 25 10 25 min 35 2 2 0 max 35 35 14 35 parameter address access time t oh t lz
p4c147 page 4 of 10 document # sram103 rev a notes: 9. ce and we must be low for write cycle. 10. if ce goes high simultaneously with we high, the output remains in a high impedance state. -10 timing waveform of write cycle no. 1 ( we we we we we controlled) (9) timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (9) sym. t wc t cw t aw t as t wp t ah t dw t dh t wz t ow parameter chip enable time to end of write address valid to end of write address set-up time write pulse width address hold time from end of write data valid to end of write data hold time write enable to output in high z output active from end of write min 10 8 8 0 8 0 5 0 0 max 5 -12 min 12 10 10 0 10 0 6 0 0 max 6 -15 min 15 12 12 0 12 0 7 0 0 max 7 -20 min 20 15 15 0 14 0 9 0 0 max 9 -25 min 25 20 20 0 15 0 12 0 0 max 12 ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) -35 min 35 25 25 0 18 0 15 0 0 max 15 unit ns ns ns ns ns ns ns ns ns ns write cycle time 11. write cycle time is measured from the last valid address to the first transition address.
p4c147 page 5 of 10 document # sram103 rev a input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce ce ce ce ce we we we we we output power standby h x high z standby read l h d out active write l l high z active truth table ac test conditions figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: due to the ultra-high speed of the p4c147, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance).
p4c147 page 6 of 10 document # sram103 rev a ordering information * military temperature range with mil-std-883, class b processing. n/a = not available selection guide the p4c147 is available in the following temperature, speed and package options. 10 12 15 20 25 35 commercial temperature plastic dip -10pc -12pc -15pc -20pc -25pc n/a cerdip n/a n/a -15dm -20dm -25dm -35dm side brazed dip n/a n/a -15cm -20cm -25cm -35cm lcc (290 x 430 mil) n/a n/a -15lm -20lm -25lm -35lm lcc (295 x 335 mil) n/a n/a -15lsm -20lsm -25lsm -35lsm cerpack n/a n/a -15fm -20fm -25fm -35fm cerdip n/a n/a -15dmb -20dmb -25dmb -35dmb side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb lcc (290 x 430 mil) n/a n/a -15lmb -20lmb -25lmb -35lmb lcc (295 x 335 mil) n/a n/a -15lsmb -20lsmb -25lsmb -35lsmb cerpack n/a n/a -15fmb -20fmb -25fmb -35fmb military temperature military processed* speed (ns) temperature range package
p4c147 page 7 of 10 document # sram103 rev a side brazed dual in-line package cerdip dual in-line package pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 0.960 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - 0 15 0.100 bsc d1 18 (300 mil) 0.300 bsc pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.030 0.065 c 0.008 0.018 d - 0.960 e 0.220 0.320 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - 0.100 bsc c9 18 (300 mil) 0.300 bsc
p4c147 page 8 of 10 document # sram103 rev a pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.280 0.305 d1 d2 d3 - 0.305 e 0.417 0.440 e1 e2 e3 - 0.440 e h j l 0.045 0.055 l1 0.075 0.090 l2 0.075 0.148 nd ne 0.020 ref 4 5 0.200 bsc 0.100 bsc 0.050 bsc 0.040 ref l7 18 .150 bsc .075 bsc rectangular leadless chip carrier cerpack ceramic flat packages pkg # # pins symbol min max a 0.045 0.092 b 0.015 0.022 c 0.004 0.009 d-0.540 e 0.245 0.370 e k 0.005 0.018 l 0.250 0.370 q 0.026 0.045 s-0.085 s1 0.005 - f1 18 0.050 bsc
p4c147 page 9 of 10 document # sram103 rev a pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.280 0.305 d1 d2 d3 - 0.305 e 0.345 0.365 e1 e2 e3 - 0.365 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.125 nd ne l7-1 18 .150 bsc .075 bsc 0.020 ref 4 5 0.200 bsc 0.100 bsc 0.050 bsc 0.040 ref rectangular leadless chip carrier pkg # # pins symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 0.880 0.920 e1 0.240 0.280 e 0.300 0.325 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p1 18 plastic dual in-line package
p4c147 page 10 of 10 document # sram103 rev a revisions document number : sram103 document title : p4c147 ultra high speed 4k x 1 static cmos ram rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid
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